Circuits with flip-flops are used in the digital signal processing field for storing logic states. Flip-flops are common examples of a circuit employing sequential logic, also called bistable gates, i.e., having two stable states. The flip-flop maintains its states indefinitely until an input pulse called a trigger is received. If a trigger is received, the flip-flop outputs change their states according to defined rules, and remain in those states until another trigger is received. Thus, they consist internally of a control element, which takes the logic state which is applied to its input and makes it available for evaluation at its output, and of a holding element, which maintains the state which is set. Flip-flop circuits are interconnected to form the logic gates that comprise digital integrated circuits (ICs), such as memory chips and microprocessors.
A flip-flop includes two latches, and each latch contains a memory element. FIG. 1 illustrates a circuit diagram of a prior art latch 100. The circuit 101 shows an inverter comprising transistors 103, 105 (PMOS/NMOS P14/N12) to illustrate the generation of the inverted clock signal (CPN) for latch 100 use. In operation, when the clock signal (CP) is in a low state, data that is on the data input (D) passes through the switch 110 (formed by transistors 112, 114 N0/P0), sets the storage node (S), passes through the inverter 120 (formed by transistors 122, 124 P10/N8) and the inverter 130 (formed by transistors 132, 134 P15/N13), resulting in the data output (Q) having the same value as the input D. Thus, the latch 100 is transparent, and data passes through. When the clock signal CP goes to a high state, the input switch 110 will no longer pass the data, and the data is stored through a memory element 140 comprising the inverter 120, the inverter 150 (formed by transistors 152, 154 P12/N10), and the switch 160 (formed by the transistors 162, 164 N11/P13). In this manner, the latch is ‘latched,’ and the data stored on the storage node will be present on the output regardless of how data changes on the input. If the supply voltage VDD is turned off, the inverters 120, 150 in the core will lose their power, and data is lost. Such volatility can be undesirable.
Accordingly, a need exists for a nonvolatile latch. The present invention addresses such a need.